//写操作模块
module write_operate (
    input   wire                clk_50m,
    input   wire                rst_n,
    output  reg                 wrreq,
    output  reg     [15:0]      data,
    input   wire                wrempty,        //空标志位，触发写动作，一旦开始，此信号又会消失
    input   wire                wrfull
);

    //方法一：定义一个状态保持寄存器
    //方法二：使用状态机
    reg             [1:0]       cs = 0;         //0:停止写，1:写状态

    always @ (posedge clk_50m or negedge rst_n) begin
        if (!rst_n) begin
            cs <= 0;
            wrreq <= 0;
            data <= 0;
        end
        else
            case (cs)
                0   : begin
                        if (wrempty) begin
                            cs <= 1;
                            wrreq <= 1;
                            data <= data + 2;
                        end
                        else cs <= 0;
                    end
                1   : begin
                        if (wrfull) begin
                            cs <= 0;
                            wrreq <= 0;
                            data <= 0;
                        end
                        else begin
                            cs <= 1;
                            wrreq <= 1;
                            data <= data + 2;
                        end
                default: ;
            endcase
    end
    
endmodule 